1. Field
Embodiments described herein generally related to integrated circuit (IC) device packaging technology.
2. Background
Die-up plastic ball grid array packages were first introduced by Motorola and were called Overmolded Plastic Pad Array Carriers (OMPAC) (See, B. Freyman, and R. Pennisi, “Overmolded Plastic Pad Array Carriers (OMPAC): A Low Cost, High Interconnect Density IC Packaging Solution for Consumer and Industrial Electronics”, Electronic Components and Technology Conference, IEEE, pp. 176-182, 1991). Commonly known as a PBGA package, the plastic ball grid array package features a plastic printed circuit board (substrate) typically made of BT (Bismaleimide Triazine) resins or FR4 materials.
Conventional PBGA packages have the drawbacks of (1) poor thermal performance, (2) no EMI protections, (3) thick top mold and overall package profile height, (4) small ratio of die-to-package size since the mold cap must be clamped to the package substrate for molding, and (5) large package body size. Both the resin substrate and the plastic molding compound materials have low thermal conductivity values molding compound). Since the die is surrounded entirely by materials with poor heat conduction properties, the heat generated on the IC die is trapped within the PBGA package. The temperature of the IC die has to rise to very high values above the environment temperature in order to release the trapped heat to the environment.
Both the resin substrate and the plastic molding compound materials are transparent to electromagnetic radiation. Consequently, electromagnetic radiation generated from the IC device will escape from the package and enter the electronic system and interfere with other electronic components. The IC device is also unprotected from electromagnetic radiation emitted from other components inside as well as outside the electronic system.
The mold thickness of the joint Electron Device Engineering Council (JEDEC) standard PBGA packages is 1.17 mm. At a mold thickness of 1.17 mm, the overall heights of PBGA packages commonly are in the range of 1.5 mm˜2.5 mm. For mobile applications such as hand-held communication devices (cell phones, global positioning devices, watch-size communication devices, etc.), mobile multimedia (video/audio) players, wireless personal area networking devices such as Bluetooth headset, and flash memory devices such as memory cards, paper-thin packages are desirable to enable small electronic devices for these applications.
A mold chase with multi-cavity mold caps is used for mold encapsulation of JEDEC standard PBGA packages. Each individual substrate unit in a substrate strip or panel has a corresponding mold cap for molding using thermoset molding epoxy. This is necessary in order to clamp the mold chase to the package substrate peripheral in a transfer molding process. The periphery of the substrate top surface is exposed (not covered by the molding compound). Both the IC die and wirebond interconnections from the die edge to the package substrate must be placed within the mold cavity. Additionally, the IC die and the wirebond must be kept at a sufficient distance away from the inner walls of the mold cavity to allow mold flow and avoid wire sweeping. Consequently, the size of the IC die is confined by the size of the mold cap (mold cavity). For a given size of substrate, the allowed maximum size of the die is substantially smaller than the size of the substrate.
Conventional PBGA packages are typically large in body size, ranging from 19 mm×19 mm and above. A large package size is undesirable for mobile applications where bulky electronic components make for bulky devices. To reduce package size, chip scale packages have been developed where the size of the IC die is very close to the size of the package. In addition to the smaller solder balls and smaller ball pitch used for a fine pitch ball grid array (FBGA) package, the mold thickness is reduced to 0.25 mm˜0.7 mm. The molding compound covers the entire top surface of FBGA package that enables the increase of die size to substrate size ratio.
Dreiza et al. reported stacked packages using wirebonded bottom PSvfBGA (package stackable very thin fine pitch BGA) (M. Dreiza, A, Yoshida, J. Micksch, and L. Smith, Implement Stacked Package-on-Package Designs, http://www.eetasia.com/ART—8800379158—480100_TA_db7b00bf.HTM). The package-to-package interconnection is facilitated by mounting the top ball grid array (BGA) package to the substrate of the bottom package. The bottom package has exposed land pads on the substrate top surface which provide contact with the solder balls on the top BGA package. The exposed solder ball land pads are located along the periphery of the substrate top and surround the package molding compound. The top package can be attached to the bottom package using conventional reflow surface mount processes. The PSvfBGA provides the added advantage of reducing overall package stack height by placing the IC die of the bottom package within a window opening in the substrate center.
Because the solder ball land pads on the bottom package substrate top must be exposed for stacking the top package, the IC die of the bottom package must be encapsulated with a mold cavity (mold cap) to define the extent of the mold and prevent the mold compound from covering or contaminating the ball pads. Consequently, the die size in the bottom package can not be too large in order for both the die and bond wires to fit into the mold.
Improvements in EMI shielding have been made for BGA type of IC packages. U.S. Pat. No. 7,432,586, issued Oct. 7, 2008, and commonly owned with the present disclosure, proposes a metal shield integrated into a die-up wire bond ball grid array (BGA) package for both EMI isolation and thermal improvement. The disclosure of the '586 patent is incorporated herein by reference in its entirety as though set forth in full below. In the design disclosed in the '586 patent, an IC die is enclosed inside a top metal structure and a bottom metal structure. The top metal structure is shaped like an inverted cup. The top metal structure is in contact with a flat metal structure at the bottom portion of the mold body. An IC die is mounted on the flat bottom metal structure. Ambient EMI radiations are blocked by the grounded top and metal structures from interfering with the operation of the IC die. This design provides an enclosed metal box, a Faraday cage, for EMI shielding within a wire bond BGA package. For a flip chip die, however, the metal box structure disclosed in the '586 patent cannot provide an interconnection between the IC die and the substrate.
Ideally in package-on-package devices, both the bottom and top packages in the package stack are the same size and type of packages with exactly the same structure (same size of die, same substrate or die carrier design and structure, etc.) in order to minimize stress match between packages. However, interconnections between stacked wirebond packages are most easily made between the package substrates. To provide a vertical package interconnection, the bottom package substrate is partially exposed along the substrate periphery. A transfer mold process with a mold cap cavity smaller than the substrate size must be used. This requirement to partially expose the substrate top surface for package-to-package interconnection purposes limits the bottom package to a PBGA package, or package with similar features. In order to minimize stress mismatch, the top package is also limited to a transfer molded BGA package such as a PBGA package. For an overmold package such as a fine pitch ball grid array (FBGA), it can only be used for the top package because the FBGA substrate top is entirely covered by the mold compound.
Moreover, stacking of FBGA packages can be desirable to reduce the overall footprint size of stacked packages and to reduce overall stacking height (or increase the number of packages in a package stack for as given height) by taking advantage of chip scale design feature and thin mold chase of the FBGA package.
The present disclosure will now be described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.